1. Field of the Invention
The present invention relates to a method for fabricating a capacitor in a semiconductor device, and more particularly to a method for fabricating a capacitor in a semiconductor device having a dual dielectric film structure composed of Ta2O5/Si3N4, and a capacitor fabricated thereby.
2. Description of the Prior Art
Recently, as high integration of memory products has become accelerated following the development of microscopic fabrication process technologies for semiconductors, unit cell area is largely decreased and driving voltage has been lowered considerably.
However, the necessary capacity of the capacitor for the driving of memory elements is required to increase above 25 fF per cell so as to suppress the contraction of the refresh time and to prevent the occurrence of soft errors, despite the reduction of the cell area.
Accordingly, recently a three dimensional type electrical charge storage electrode with hemispheric structure having a large surface area has been used for DRAM capacitor elements which utilize a nitride layer with a nitride layer/oxide layer (N/O) structure as a dielectric, and the height of the capacitor has been increased steadily.
Meanwhile, a depth of focus is not assured in the following exposure process due to the differences of height produced between a cell region and a peripheral circuit region when the height of the capacitor increases, which results in a bad effect upon the integration process which follows the wiring process.
As stated above, conventional N/O capacitor element comes to a limitation in assuring charging capacity of a capacitor requisite for future DRAM products such as those are over 256 M. As a result, as shown in FIGS. 1A to 1D, a capacitor made of Ta2O5 has been actively developed.
Referring to FIGS. 1A to 1D, a conventional fabricating method for a capacitor in a semiconductor device using a Ta2O5 dielectric film will be described as follows.
FIGS. 1A to 1D are sectional views illustrating steps of a fabricating method for a capacitor in a semiconductor device in accordance with the prior art.
According to the fabricating method of the prior art for a capacitor for a semiconductor device, as shown in FIG. 1A, an interlayer insulating film 3 is first deposited over a semiconductor substrate 1, photo-sensitive materials are distributed on the interlayer insulating film, and a first photo-mask (not shown) for making plug contacts is formed by carrying out an exposure process and a developing process using photolithography technology, and carrying out a selective patterning of the interlayer insulating film.
Then, a plug contact hole 5 exposing a portion of the semiconductor substrate 1 is formed by patterning the interlayer insulating film 3 with a first photo-mask (not shown), and then the first photo-mask is removed.
Subsequently, conductive materials are deposited on the plug contact hole 5 and the first interlayer insulating film 3, and a chemical-mechanical polishing (CMP) is carried out, resulting in the formation of a contact plug 7 in the plug contact hole 5.
Referring to FIG. 1B, a second interlayer insulating film 9 is deposited on an entire surface of the semiconductor substrate 1, and then photo-sensitive materials are distributed on the second interlayer insulating film 9, and a second photo-mask (not shown) for making plug contacts is formed by carrying out an exposure process and a developing process using photolithography technology and carrying out a selective patterning of the second interlayer insulating film.
Then, a contact hole 11 defining a lower electrode region is formed in the second interlayer insulating film 9 over the contact plug 7 by patterning of the second interlayer insulating film 9 with the second photo-mask (not shown), and then the second photo-mask (not shown) is removed.
Subsequently, a doped polysilicon layer (not shown) is deposited on the second interlayer insulating film 9 inclusive of the contact hole 11, and photo-sensitive materials are distributed thereon. In this instance, the production process of the polysilicon layer (not shown) is carried out by utilizing a LPCVD chamber so as to employ a capacitor module with a cylindrical structure or a concave structure as a lower electrode.
Then, a lower electrode 13 of cylindrical shape is formed by removing the photo-sensitive materials and the second interlayer insulating film 9 remaining after the CMP processing of the photo-sensitive materials and the doped polysilicon layer (not shown), the lower electrode being contacted with the contact plug 7. In this instance, a lower electrode having a concave structure can be formed in place of the cylindrical structure. In the above case, it is possible to remove just the photo-sensitive materials in order to form a lower electrode in the shape of concave structure after carrying out the CMP processing of the photo-sensitive materials and the doped polysilicon layer (not shown).
FIG. 1C shows the lower electrode 13 remaining after the removal of the photo-sensitive materials.
Referring now to FIG. 1D, a Ta2O5 thin film 15 is deposited on the lower electrode 13 and a TiN film for an upper electrode 17 is deposited on the thin film 15, thereby fabricating a capacitor in a semiconductor device. Furthermore, a doped poly-silicon layer, which functions as a buffer layer, can be deposited on the upper electrode 17 so as to secure structural stability and enhance the endurance property of the upper electrode against the thermal or electrical influences.
However, according to the above-noted prior art, vacancy atoms Ta arising from the differences of the composition ratio between Tantalum (Ta) and Oxygen (O) exist in the thin film, because the Ta2O5 thin film has an unstable stoichiometry.
Furthermore, carbon atoms and carbon compounds (C, CH4, C2H2, etc), which are impurities, and water (H2O) exist together in the thin film, due to reaction of the organic compound Ta(OC2H5)5, which is a precursor of Ta2O5, with O2 (or N2O) gas at the time of the formation of the thin film.
As a result, leakage current increases due to carbon atoms, ions and radicals that exist as impurities in the Ta2O5 thin film, and the dielectric properties become deteriorated and damaged.
As regards an Si3N4 (ε=7) dielectric film which is deposited by using DCS (Di-Chloro-Silane) gas, because the dielectric ratio is so low that it is limited in use as capacitor dielectric film of highly integrated semiconductor products, wherein a microscopic wiring process is employed for elements such as those below 0.16 μm, therefore a Ta2O5 (ε=25) dielectric film with a bigger dielectric ratio than previously has come to be employed.
However, as stated above, although the dielectric ratio of the Ta2O5 thin film is big itself, during the high temperature oxidation process which follows the deposition of Ta2O5 in the fabrication process of a capacitor, an interface oxide film (Si2O, ε=3.85) having a low dielectric ratio is deposited on the surface of a polysilicon layer, which functions as a lower electrode, so as to solve the problems which originate from the Ta2O5 thin film itself. Therefore, the thickness of the oxidation film can not be lowered to below 30 Å, resulting in limitations in achieving a large charging capacity for a capacitor.